library IEEE;
use IEEE.std_logic_1164.all;

entity Test_irq_ctrl is
end entity;


architecture test of Test_irq_ctrl is
	signal Clk: std_ulogic := '0';
	signal IRQ: std_ulogic := '0';
	signal A  : std_ulogic_vector(1 downto 0) := "00";
	signal Din: std_ulogic_vector(7 downto 0) := "00000000";
	signal Dout:std_ulogic_vector(7 downto 0) := "00000000";
	signal RW : std_ulogic := '0';
	signal CS : std_ulogic := '0';
	signal IntSrc:std_ulogic_vector(7 downto 0) := "00000000";
	signal Reset: std_ulogic := '0';
	
	component irq_ctrl is 
	port (
	   Reset: in std_ulogic;--active high
		IRQ: out std_ulogic; -- active high
		IntSrc : in std_ulogic_vector(7 downto 0);
		Address: in std_ulogic_vector(1 downto 0); -- just an arbitrary number, I only need 1 register at the moment
		Clock : in std_ulogic;
		DataIn: in std_ulogic_vector;
		DataOut: out std_ulogic_vector;
		RW    : in std_ulogic;
		CS    : in std_ulogic
	);
	end component irq_ctrl;

begin
	controller: component irq_ctrl
		port map (
			Reset => Reset,
			Clock => Clk,
			IRQ => IRQ,
			Address => A,
			DataIn => Din,
			DataOut => DOut,
			RW    => RW,
			CS    => CS,
			IntSrc => IntSrc
		);
	
	A <= "00";
	Reset <= '1', '0' after 1 us;
	
	Clk <= not Clk after 10 ns;
	
end;